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Hi-performance Regulator IC Series for PCs
2ch Switching Regulators for Desktop PC
BD9540EFV
No.09030EBT07
Description BD9540EFV is a 2ch switching regulator synchronous controller that can generate low output voltages (0.75V to 5.5V). High efficiency for the switching regulator can be achieved due to its external N-MOSFET power transistor. The IC also 3 TM incorporates a new technology called H Reg , a Rohm proprietary control method which facilitates ultra-high transient response against changes in load. For protection and ease of use, the IC also incorporates soft start, and short circuit protection with timer latch functions. This switching regulator is designed for DRAM and power supplies for graphics chips. Features 3 TM 1) 2ch H Reg DC/DC converter synchronous controller 2) Thermal Shut Down (TSD), Under-Voltage Lock-Out (UVLO), Adjustable Over Current Protection (OCP) : detected Low side FET Ron, Over Voltage Protection (OVP), Short Circuit Protection (SCP) built-in 3) Soft start function to minimize rush current during startup 4) HTSSOP-B28 package 5) Built-in 5V power supply for FET driver 6) Integrated bootstrap diode Applications LCD-TV, Game Consoles, Desktop PCs Maximum Absolute Ratings (Ta=25) Parameter Input Voltage BOOT Voltage BOOT-SW Voltage HG-SW Voltage LG Voltage Output Voltage Output Feedback Voltage 5VReg Voltage Current Limit Setting Voltage Logic Input Voltage 1 Logic Input Voltage 2 Power dissipation 1 Power dissipation 2 Power dissipation 3 Power dissipation 4 Operating Temperature Range Storage Temperature Range Junction Temperature
Symbol VIN BOOT1,BOOT2 BOOT1-SW1, BOOT2-SW2 HG1-SW1, HG2-SW2 LG1, LG2 VOUT1, VOUT2 FB1, FB2 5VReg ILIM1, ILIM2 EN1, EN2 CTL1, CTL2 Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax
Limit 24*1 30*1 7*1 7*1 5VReg 7*1 5VReg 7*1 5VReg 24*1 7*1 1.45*2 1.85*3 3.30*4 4.70*5 -20+100 -55+150 +150
Unit V V V V V V V V V V V W W W W
*1 Not to exceed Pd. *2 Reduced by 11.6mW for each increase in Ta of 1 over 25 (when mounted on a board 70.0mmx70mmx1.6mm Glass-epoxy PCB, 1layer, no copper foil area.) *3 Reduced by 14.8mW for increase in Ta of 1 over 25. (when mounted on a board 70.0mmx70mmx1.6mm Glass-epoxy PCB, 2layers, copper foil area : 15mmx15mm.) *4 Reduced by 26.4mW for increase in Ta of 1 over 25. (when mounted on a board 70.0mmx70mmx1.6mm Glass-epoxy PCB, 2layers, copper foil area : 70mmx70mm.) *5 Reduced by 37.6mW for increase in Ta of 1 over 25. (when mounted on a board 70.0mmx70mmx1.6mm Glass-epoxy PCB, 4layers, copper foil area : 70mmx70mm.)
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1/17
2009.04 - Rev.B
BD9540EFV
Operating Conditions (Ta=25) Parameter Input voltage BOOT voltage SW Voltage BOOT-SW voltage Logic Input Voltage 1 Logic Input Voltage 2 Output Voltage MIN ON Time
Technical Note
Symbol VIN BOOT1, BOOT2 SW1, SW2 BOOT1-SW1, BOOT2-SW2 EN1, EN2 CTL1, CTL2 VOUT1, VOUT2 tonmin
Min. 7.5 4.5 -0.7 4.5 0 0 0.7 -
Max. 20 25 20 5.5 20 5.5 5.5 100
Unit V V V V V V V ns
*This product should not be used in a radioactive environment. *The range of the VOUT is limited by the voltage between VIN and VOUT.
Electrical characteristics (Unless otherwise noted, Ta=25 VCC=5V, VIN=12V, VEN1=VEN2=3V, Vout1=1.5V, Vout2=1.05V) Limit Parameter Symbol Unit Condition Min. Typ. Max. [General] VIN Bias Current IIN 1.6 2.5 mA VIN Standby Current IIN_stb 0 10 A VEN1=VEN2=0V EN Low Voltage 1,2 VEN_low1,2 GND 0.3 V EN High Voltage 1,2 VEN_high1,2 2.2 20 V EN Bias Current 1,2 IEN1,2 1.5 5.0 A VEN1=VEN2=3V [5V Linear Regulator] 5VReg Standby Voltage 5Vreg_stb 0.1 V VEN1=VEN2=0V VIN=7.5V to 20V 5VReg Output Voltage 5VReg 4.8 5.0 5.2 V Ireg=0mA to 10mA Maximum Current IReg 50 mA [Under-Voltage Lock-Out] 5VReg Threshold Voltage 5Vreg_UVLO 3.75 4.20 4.65 V 5VReg:Sweep up 5VReg Hysteresis Voltage d5Vreg_UVLO 100 160 220 mV 5VReg:Sweep down [OVP Block] FB Threshold Voltage 1 FB_OVP1 0.92 1.02 1.12 V FB Threshold Voltage 2 FB_OVP2 0.80 0.90 1.00 V OVP delay time tOVP 1.7 s [H3RegTM Control Block] ON Time1 ton1 290 390 490 ns MIN OFF Time 1 toffmin1 200 380 ns ON Time 2 ton2 110 210 310 ns MIN OFF Time 2 toffmin2 200 380 ns [FET Block] HG High side ON Resistance 1,2 RHGhon1,2 5.5 11 HG Low side ON Resistance 1,2 RHGlon1,2 2.5 5 LG High side ON Resistance 1,2 RLGhon1,2 4 8 LG Low side ON Resistance 1,2 RLGlon1,2 2 4 [Over Current Protection Block] Current Limit Vilim1,2 80 100 120 mV RILIM=100k Threshold Voltage 1,2 [Output Voltage Detection Block] FB1 threshold(REF1) Voltage1 FB1-1 0.769 0.781 0.793 V CTL1=0V, CTL2=0V FB1 threshold(REF1) Voltage2 FB1-2 0.802 0.814 0.826 V CTL1=5V, CTL2=0V FB1 threshold(REF1) Voltage3 FB1-3 0.839 0.851 0.863 V CTL1=0V, CTL2=5V FB1 threshold(REF1) Voltage4 FB1-4 0.738 0.750 0.762 V CTL1=5V, CTL2=5V FB2 threshold(REF2) Voltage FB2 0.738 0.750 0.762 V CTL Low Voltage 1,2 VCTL_low1,2 GND 0.5 V CTL High Voltage 1,2 VCTL_high1,2 VCC-0.5 VCC V FB1/2 Input Current IFB1,2 -1 1 A VOUT Discharge Current IVOUT1,2 5 10 mA VOUT=1V, EN=0V [SCP Block] REF1,2x REF1,2x REF1,2x Threshold Voltage 1,2 Vthscp1,2 V 0.60 0.70 0.80 SCP delay time tSVP 28 s
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2/17
2009.04 - Rev.B
BD9540EFV
Block Diagram
VIN
Technical Note
23
VIN
22
5VReg
5VReg
VOUT1 VOUT1
4
Thermal TSD Protection EN1/UVLO TSD/OVP 5VReg
VIN BOOT1
1 28 27
HG1 SW1 LG1
VOUT1
EN1
Soft Start
SS1 REF1 SS1
+ +
H Reg Controller Block
3
TM
R S
Q SW1
Driver OCP Circuit
5VReg
26
FB1
5VReg
5
-
21
UVLO ILIM1 SCP TSD
OVP
25
VCC EN1 EN2
3 12
1.02 FB1
+
PGND1 ILIM1
OVP1 EN1
+ REF1x0.7 FB1 REF2x0.7 FB2
24
Logic Input
Reference Block
REF2 BG
SCP UVLO OVP OVP2 Delay
+ -
EN2
5VReg
CTL1 VOUT2 CTL2 VOUT2
8
DAC
9
REF1
0.90 FB2 VIN
3 TM
+
-
VIN BOOT2
14
11
EN2/UVLO TSD/OVP
15 16
HG2 SW2 VOUT2
EN2
Soft Start
SS2 REF2 SS2 UVLO ILIM2 SCP TSD
+ +
H Reg Controller Block
R S
Q SW2 OCP
Driver Circuit
5VReg
17
LG2
10
FB2
OVP
18
7
20
GND
TEST
ILIM2
19
PGND2
Pin Configuration
BOOT1 1 NC EN1 2 3
28 HG1 27 SW1 26 LG1 25 PGND1 24 ILIM1
VOUT1 4 FB1 NC GND CTL1 CTL2 5 6 7 8 9
BD9540EFV
23 VIN 22 5VReg 21 VCC 20 TEST 19 ILIM2 18 PGND2 17 LG2 16 SW2 15 HG2
FB2 10 VOUT2 11 EN2 12 NC 13 BOOT2 14
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3/17
2009.04 - Rev.B
BD9540EFV
Pin Function PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 reverse
Technical Note
PIN name BOOT1 NC EN1 VOUT1 FB1 NC GND CTL1 CTL2 FB2 VOUT2 EN2 NC BOOT2 HG2 SW2 LG2 PGND2 ILIM2 TEST VCC 5VReg VIN ILIM1 PGND1 LG1 SW1 HG1 FIN HG Driver Power Supply Pin 1 Non connection Pin
PIN Function
Enable Input Pin 1 (00.3V:OFF, 2.220V:ON) Output Voltage Sence Pin 1 Output Voltage Feedback Pin 1 Non connection Pin Sense GND 1ch Reference Voltage Setting Control Pin 1:See P12/17 1ch Reference Voltage Setting Control Pin 2:See P12/17 Output Voltage Feedback Pin 2 Output Voltage Sense Pin 2 Enable Input Pin 2 (00.3V:OFF, 2.220V:ON) Non connection Pin HG Driver Power Supply Pin 2 High side FET Gate Driver Pin 2 High side FET Source Pin 2 Low side FET Gate Driver Pin 2 Power GND for 2ch 2ch OCP Setting Pin Connect to GND Pin Power Supply Input Pin Reference Voltage Inside IC (5V Voltage Output) Battery Voltage Sense Pin 1ch OCP Setting Pin Power GND for 1ch Low side FET Gate Driver Pin 1 High side FET Source Pin 1 High side FET Gate Driver Pin 1 Exposed Pad, Connect to GND
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4/17
2009.04 - Rev.B
BD9540EFV
Reference Data
Technical Note
VOUT2 50[mV/div]
VOUT2 50[mV/div]
VOUT1 50[mV/div]
SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] (2s/div)
SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] (2s/div)
SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] (2s/div)
Fig.1 Transient Respnse (VIN=12V VOUT2=1.05V)
Fig.2 Transient Respnse (VIN=12V VOUT2=1.05V)
Fig.3 Transient Respnse (VIN=12V VOUT1=3.3V)
VOUT1 50[mV/div]
EN 50[V/div] 1msec(typ)
EN 50[V/div] 1msec(typ)
SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div]
VOUT 0.5[V/div] SW 10[V/div] IL 2[A/div]
VOUT 0.5[V/div] SW 10[V/div] IL 2[A/div]
(2s/div)
Fig.4 Transient Respnse (VIN=12V VOUT1=3.3V)
130
HG, LG 20[V/div]
Fig.5 VOUT wake up (Io=0A)
100
Fig.6 VOUT wake up (Io=4A)
Vo=1.8V
120 VILIM [mV] 110 100 90 80
RILIM=100k
80 Efficiency [%] 60 40 20 0
Vo=1.2V
VOUT 1[V/div]
28sec(typ)
IL 5[A/div]
VIN=12V VMOSFET:MP6K61
-20
0
20
40 Ta []
60
80
100
0.01
0.1 IOUT [A]
1
10
Fig.7 OCP and SCP
2.5 2 1.5 1 0.5 0 -20 0 20 40 Ta [] 60 80 100
IIN_STB [A] 10
Fig.8 Ta-VILIM
2.5
Fig.9 IOUT-Efficiency
8
2
IIN [mA]
4
IIN [mA]
6
1.5
1
VIN=12V VCC=VREG5V EN1=EN2=3V
2
VIN=12V VCC=VREG5V EN1=EN2=0V
0.5
VCC=VREG5V EN1=EN2=3V
0 5 10 VIN [V] 15 20
0 -20 0 20 40 Ta [] 60 80 100
0
Fig.10 Ta-IIN
Fig.11 Ta-IIN_STB
Fig.12 VIN-IIN
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5/17
2009.04 - Rev.B
BD9540EFV
Reference Data
10
5.2
6 5
Technical Note
8 IIN_STB [A]
VCC=VREG5V EN1=EN2=0V
5VREG [V]
5.1
4 5VREG [V]
6
5
3 2
4
2
4.9
1
0 0 4 8 12 VIN [V] 16 20
4.8 -20 0 20 40 Ta [] 60 80 100
0 0 4 8 VIN [V] 12 16 20
Fig.13 VIN-IIN_STB
25
6
Fig.14 Ta-5VREG
6 5 4
Fig.15 VIN-5VREG
20
5
4
VOUT1[V]
3
10
2
5
1
0 0 4 8 12 16 20 VEN[V]
0 7.5 10 12.5 15 17.5 20
VOUT2[V}
IEN [A]
15
3 2 1 0 7.5 10 12.5 15 17.5 20
VIN[V]
VIN[V]
Fig.16VENIEN
Fig.17 VIN-VOUT1
Fig.18 VIN-VOUT2
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6/17
2009.04 - Rev.B
BD9540EFV
Technical Note
Pin Descriptions EN1 (3 pin) / EN2 (12 pin) When the input voltage on the EN pin reaches at least 2.2V, the switching regulator becomes active. At voltages less than 0.3 V, the switching regulator becomes inactive, and the input current drops to 10A or less. Thus the IC can be controlled from 2.5V, 3.3V or 5V power supplies. 5VReg (22 pin) 5.0V reference voltage output pin. If at least 2.2V is supplied to either the EN1 or EN2 pin, the reference output is switched on. This pin supplies 5.0V at up to 10mA. Inserting a 4.7F capacitor (with a X5R or X7R rating) between the 5VReg and GND pins is recommended. ILIM1 (24 pin) / ILIM2 (19 pin) The IC monitors the voltage between the SW pin and PGND pin as a control for the output current protection (OCP) mechanism. The voltage at which OCP engages is determined by the resistance value connected to the ILIM pin. This also allows for compatibility with FETs of various RON values. VIN (23 pin) The IC determines the duty cycles internally based upon the input voltage on this pin. Therefore, variations in voltage on this pin can lead to highly unstable operation. This pin also acts as the voltage input to the internal switching regulator block, and is sensitive to the impedance of the power supply. Attaching a bypass capacitor or RC filter on this pin as appropriate for the application is recommended. BOOT1 (1 pin) / BOOT2 (14 pin) This pin supplies voltage used for driving the high-side FET. Maximum absolute ratings are 25V from GND and 5.5V from SW. BOOT voltage swings between VIN + 5VReg and 5VReg during active operation. HG1 (28 pin) / HG2 (15 pin) This pin supplies voltage used for driving the gate of the high-side FET. This voltage swings between BOOT and SW. High-speed gate driving for the high side FET can be achieved due to its low on-resistance (5.5 when HG = high, 2.5 when HG = low) of the driver. SW1 (27 pin) / SW2 (16 pin) This pin acts as the source connection to the high-side FET. Maximum absolute rating is 20V from GND. SW voltage swings between VIN and GND. LG1 (26 pin) / LG2 (17 pin) This pin supplies voltage used for driving the gate of the low-side FET. This voltage swings between VDD and PGND. High-speed gate driving for the low-side FET can be achieved due to its low on-resistance (4 when LG = high, 2 when LG = low) of the driver. PGND1 (25 pin) / PGND2 (18 pin) This pin acts as the ground connection to the source of the low-side FET. GND (7 pin) This is the ground pin for all internal analog and digital power supplies. VOUT1 (4 pin) / VOUT2 (11 pin) This is the output voltage sense pin; this pin features an integrated discharge FET used to discharge the output capacitor when status is set to OFF. FB1 (5 pin) / FB2 (10 pin) This is the output feedback pin. While the internal reference voltage of channel 2 is fixed at 0.750V, the internal reference voltage of channel 1 is adjustable depending on the input conditions of the CTL1 and CTL2 pins. Vcc (21 pin) This is the power supply pin for all internal circuitry. This pin can be supplied directly by a 5V source, or via an RC filter (10 , 0.01F) from the 5VReg pin. CTL1 (8 pin) / CTL2 (9 pin) These pins allow for the adjustment of the internal voltage reference (REF1) for channel 1. The pins recognize logic High at VCC-0.5 V or above, and logic Low at 0.5 V or below. Refer to the voltage adjustment table for REF1 on page 12.
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7/17
2009.04 - Rev.B
BD9540EFV
Technical Note
Explanation of Operation The BD9540EFV is a 2ch switching regulator controller incorporating ROHM's proprietary H3RegTM CONTROLLA control system. When VOUT drops due to a rapid load change, the system quickly restores VOUT by extending the TON time interval. H3RegTM control (Normal operation) FB REF
When FB falls below the threshold voltage (REF), a drop 3 TM is detected, activating the H Reg CONTROLLA system. VOUT 1 x VIN f
HG LG
tON=
[sec](1)
HG output is determined by the formula above. (See P13) LG output operates until FB voltage falls below REF voltage after HG becomes OFF.
(VOUT drops due to a rapid load change) FB REF When FB (VOUT) drops due to a rapid load change, and the voltage remains below REF after the programmed tON time interval has elapsed, the system quickly restores VOUT by extending the tON time, improving transient response.
Io HG
LG
Timing Chart Soft Start Function Soft start is utilized when the EN pin is set high. Current control takes effect at startup, enabling a moderate "ramping start" on the output voltage. Soft start time is 1msec. And input current is determined via formula (2) below.
EN 1msec
VOUT Rush current: IIN IIN = CoxVOUT 1ms [A] (2)
(Co: All capacitors connected with VOUT)
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8/17
2009.04 - Rev.B
BD9540EFV
Timing Chart Over current protection circuit
Technical Note
tON HG
tON
tON
tON
During normal operation, when FB falls below REF, HG switches high during for the period of time tON (P8). However, if the current of the low-side FET exceeds the ILIMIT threshold, HG will switch off until it becomes below ILIMIT.
LG
IL
ILIMIT
Timer Latch Type Short Circuit Protection
REFx0.7 FB 28s HG LG Short protection engages when output falls to or below REF x 0.7. When the programmed time period (28s) elapses, output is latched off to prevent damage to the IC. Output voltage can be restored either by reconnecting the EN pin or disabling UVLO.
EN/UVLO
Output Over Voltage Protection
OVP threshod voltage
VOUT
1.7s
HG
When output voltage rises to or above the OVP threshold voltage (1ch:1.02V, 2ch:0.9V), output over-voltage protection engages after the set time (1.7s) has elapsed. During this protection period, the low-side FET opens completely for maximum reduction of output voltage (LG = high, HG = low). Output voltage can be restored either by reconnecting the EN pin or disabling UVLO.
LG Switching
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9/17
2009.04 - Rev.B
BD9540EFV
External Component Selection 1. Inductor (L) selection
Technical Note
IL
The inductance value has a major influence on output ripple current. As formula (3) below indicates, the greater the inductance or switching frequency, the lower the ripple current. IL= (VIN-VOUT)xVOUT LxVINxf [A](3)
VIN
HG SW
IL VOUT L Co
The proper output ripple current setting is about 30% of maximum output current. IL=0.3xIOUTmax. [A](4) L= (VIN -VOUT)xVOUT ILxVINxf [H](5)
LG
(IL: output ripple current; f: switch frequency) Output Ripple Current Passing a current larger than the inductor's rated current will cause magnetic saturation in the inductor and decrease system efficiency. When selecting an inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor's rated current value. To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance. 2. Output Capacitor (CO) Selection
VIN
HG SW L LG VOUT ESR ESL Co
When determining a proper output capacitor, be sure to factor in the equivalent series resistance and equivalent series inductance required to set the output ripple voltage to 20mV or more. Also, make sure the capacitor's voltage rating is high enough for the set output voltage (including ripple). Output ripple voltage is determined as in formula (6) below. VOUT=ILxESR+ESLxIL/TON(6) (IL: Output ripple current; ESR: CO equivalent series resistance, ESL: equivalent series inductance)
Output Capacitor
Also, give due consideration to the conditions in formula (7) below for output capacitance, bearing in mind that output rise time must be established within the soft start time frame: Co 1msx(Limit-IOUT) VOUT (7) Tss: Soft start time Limit: Over current detection IOUT : Output current
Note: an improper output capacitor may cause startup malfunctions. 3. Input Capacitor (Cin) Selection
VIN Cin HG SW L LG Co VOUT
In order to prevent transient spikes in voltage, the input capacitor selected must have a low enough ESR resistance to fully support a large ripple current on the output. The formula for ripple current IRMS is given in equation (8) below: VOUT (VIN-VOUT) VIN 2
IRMS=IOUTx
[A](8)
Where VIN=2xVOUT, IRMS= Input Capacitor
IOUT
A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
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10/17
2009.04 - Rev.B
BD9540EFV
4. MOSFET Selection
Technical Note
Main MOSFET power dissipation is computed as follows:
VIN main switch
Pmain = PRON + PGATE + PTRAN =
2 VIN VOUT xRONxIOUT2+Qg(High)xfx5VReg+ xCrssxIOUTxf (9) IDRIVE VIN
VOUT L Co
(Ron: On-resistance of FET; Qg: FET gate capacitance; f: Switching frequency; Crss: FET inverse transfer function; IDRIVE: Gate peak current) Synchronous MOSFET power dissipation is computed as follows: Psyn = PRON + PGATE = VIN-VOUT VIN xRONxIOUT2+5VRegxfxVDD (10)
synchronous switch
Qg loss is also incurred as internal power dissipation in the IC: = PIC(DRIVE) = Qg(High)xf + Qg(Low)xf x(VIN-5VReg) (11)
For example: If Qg(High) = 20nq, Qg(Low) = 50nq, f = 300kHz, PIC(DRIVE) = = 0.147W 20nx300k +50nx300k x(12-5)
5. Determining Detection Resistance
VIN The over-current protection function is controlled via the voltage detected between the SW and PGND pins - i.e., the ON-resistance of the synchronous FET. The current limit value is determined by formula (12) below: ILIM= 10k RILIM xRON [A](12)
L
SW
Co
VOUT
RILIM
PGND
(RILIM: Resistance for setting over-current protection limit, RON: Low side FET On-resistance)
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11/17
2009.04 - Rev.B
BD9540EFV
Technical Note
6. Output Voltage Setting The IC will try to maintain output voltage such that REFVFB. However, the actual output voltage will also reflect the average ripple voltage value. The output voltage is set via a resistive voltage divider between the output and the FB pin. The formula for output voltage is given in (13) below: R1+R2 R2 1 2
Output voltage=
x REF +
xILxESR(13) VIN
REF
H3RegTM CONTROLLA
R S
Q Driver Circuit
Output voltage ESR R1 Radd (for Low Ripple) R2 Cadd (for Low Ripple) C1
FB
It is recommended that R1 and C1 be connected in parallel to the FB pin. In low output ripple applications (V < 20 mV), add Radd and Cadd as shown in the above application circuit. For value settings, refer to the tool provided separately. REF voltage (for 2ch) is fixed at 0.750 V; however, REF voltage (for 1ch) can be adjusted via the CTL input conditions. REF1 voltage setting table CTL1 L H L H CTL2 L L H H REF1 0.781V 0.814V 0.851V 0.750V
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12/17
2009.04 - Rev.B
BD9540EFV
Technical Note
7. Relationship between output voltage and Ton duration Both 1ch and 2ch of BD9540EFV are synchronous rectification type of switching controllers operated at fixed-frequency. The Ton duration for each channel depends on the output voltage settings, as described by the following formulas. Ton1 = VOUT1 x2+130n [ns](14) VIN VOUT2 x0.9+130n [ns](15) VIN (1ch)
Ton2 =
(2ch)
Thus from the above Ton duration, the frequency of the applied condition is Frequency = VOUT x VIN 1 Ton [kHz](16)
However with actual applications, there exists a rising and falling time of the SW due to the gate capacitance of the external MOSFET and the switching speed, which may vary the above parameters. Thus please also verify those parameters experimentally.
8. Relationship between output current and frequency BD9540EFV is a fixed-Ton type of switching controller. When the output current increases, the switching loss of the coil and MOSFET also increases and hence the switching frequency speeds up. The loss of the coil and MOSFET is determined as Loss of coil = IOUT2 x DCR Loss of high-side MOSFET = IOUT2 x Ronh x Loss of low-side MOSFET = VOUT VIN VOUT VIN )
IOUT2 x Ronn x (1-
(Ronh : on-resistance of high-side MOSFET, Ronn : on resistance of low-side MOSFET)
Taking the above losses into the frequency equation, then T (=1/Freq) becomes T (=1/Freq) = VIN x IOUT x Ton VOUT x IOUT + + + (17)
However since the parasitic resistance of the layout pattern exists in actual applications and affects the parameter, please also verify experimentally.
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13/17
2009.04 - Rev.B
BD9540EFV
I/O Equivalent Circuits 1pin, 14pin (BOOT1, BOOT2) 3pin, 12pin (EN1, EN2)
1M
Technical Note
22pin (5VReg)
VIN
2M
HG
SW
5VReg BOOT
8pin 9pin (CTL1, CTL2)
28pin, 15pin (HG1, HG2)
BOOT BOOT
27pin, 16pin (SW1, SW2)
BOOT HG
300K SW
26pin, 17pin (LG1, LG2)
5VReg
20pin (TEST)
24pin, 19pin (ILIM1, ILIM2) 5pin, 10pin (FB1, FB2)
300K 100K
300K
21pin (VCC)
4pin, 11pin (VOUT1, VOUT2)
23pin (VIN)
400K 5VReg
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14/17
2009.04 - Rev.B
BD9540EFV
Technical Note
Operation Notes (1) Absolute Maximum Ratings Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode) when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power Supply Polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power Supply Lines In order to minimize noise, PCB layout should be designed such that separate, low-impedance power lines are routed to the digital and analog blocks. Additionally, a coupling capacitor should be inserted between all power input pins and the ground terminal. If electrolytic capacitors are used, keep in mind that their capacitance characteristics are reduced at low temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions. (6) Inter-pin Shorts and Mounting Errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by poor soldering or foreign objects may result in damage to the IC. (7) Operation in Strong Electromagnetic Fields Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in applications where strong electromagnetic fields may be present. (8) ASO - Area of Safe Operation When using the IC, ensure that operating conditions do not exceed absolute maximum ratings or ASO of the output transistors. (9) Thermal shutdown (TSD) circuit The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used after this function has activated, or in applications where the operation of this circuit is assumed. TSD ON Temp. [C] BD9540EFV 175 (typ.) Hysteresis Temp. [C] 15 (typ.)
(10)Testing on application boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC's power supply should always be turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
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15/17
2009.04 - Rev.B
BD9540EFV
Technical Note
(11) Regarding input pins of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below): When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.
Resistor Pin A Pin A
P+ N P P+
Transistor (NPN) Pin B
C B E B P P+ N C E
Pin B
N
N
Parasitic element
N
P+
N
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element
Other adjacent elements
Example of IC structure
(12)Ground Wiring Pattern When using both small-signal and large-current GND traces, the two ground traces should be routed separately but connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage. Power Dissipation
5.0
4.70W
Power dissipation :Pd [W]
4.0
3.30W
3.0
Mounted on board 70mmx70mmx1.6mm glass-epoxy PCB, 1 layer No copper foil area. j-a=86.2/W Mounted on board 70mmx70mmx1.6mm glass-epoxy PCB, 2 layers, Copper foil area : 15mmx15mm, j-a=67.6/W Mounted on board 70mmx70mmx1.6mm glass-epoxy PCB, 2 layers, Copper foil area :: 70mmx70mm, j-a=37.9/W Mounted on board 70mmx70mmx1.6mm glass-epoxy PCB, 4 layers, Copper foil area :: 70mmx70mm, j-a=26.6/W
2.0
1.85W 1.45W
1.0
0 0 25 50 75 100 125 150
Ambient temperature :Ta []
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
16/17
2009.04 - Rev.B
BD9540EFV
Ordering part number
Technical Note
B
D
9
Part No.
5
4
0
E
F
V
-
E
2
Part No.
Package EFV : HTSSOP-B28
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B28
9.70.1 (MAX 10.05 include BURR) (5.5)
28 15

Tape
+6 4 -4
0.50.15 1.00.2
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
6.40.2
4.40.1
(2.9)
( reel on the left hand and you pull out the tape on the right hand
)
1
14
0.625
1.0MAX
1PIN MARK S
+0.05 0.17 -0.03
0.850.05
0.080.05
0.08 S 0.65 +0.05 0.24 -0.04 0.08
M
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
17/17
2009.04 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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